Why Does Cadence VXL Compliance Matter?

To understand this you need to review the “Physical Design Stage”, The stage of IC Design where conception, architecture, simulation and test plans meet the real world. There are many views of creating IC products which are critical to design success. RTL, architecture, design, packaging simulation, software development and testing. Like a funnel, they all feed into the final IC Layout Design mask set. When layout is created that is to be converted to million dollar masks, many critical objects become instantiated (inserted) at different levels to comply with the needs described above.

These objects include “pCells” (programmable Cells), “Wire Segments”, Fluid and Multi Part Path Guard Rings, Pins, Labels, Boundaries, Figure Groups, Clones. All objects in any layout cell should be purposeful or removed. They are either part of the mask set or creation of final products.

So the objects remaining need to conform to VXL. This can seem like a daunting, almost useless task for schedule stressed designers.  Especially for the experienced “Block Level” custom IC layout circuit designer who has a reputation for producing work fast with very few tools.  They might not be able to see clearly, as the top-level design integrator, what this really means.   Sometimes they don’t understand the intentions of the tool makers.  They don’t clearly see the benefits “Further Down the Road” of product development.

These steps do not take long at all compared to the design work itself.  To make this clearer, I will state (what I believe) are the requirements for Virtuoso VXL (AKA: Cell View, Circuit, Macro or Block).

• All objects are accounted for. The ones which directly relate to the schematic are matched utilizing the VXL object correspondence tool.  Any other objects, like groups, clones, custom layout cells, etc. require names that make sense to why they exist in the cell view.
• Nodes are easily identifiable. Using the tool “Annotation Browser”, the designer can be certain nodes are connected properly.  As a matter of fact, if you use the annotation browser combined with VXL layout extraction tool, LVS first pass success is almost guaranteed.
• Matching schematic pins and labels all exist.  Pins are how Cadence VXL can determine hierarchical connectivity and labels are required for verification.  The axis points on labels (cross hair) should be placed on the pin.
• Figure Groups and Clones need custom names which helps communicate their intention.

Never forget that you are creating IP, not just a product for the market.  Making your physical IP easier for the next product development team keeps you ahead of the competition.