TSMC 7nm/5nm Combined Layout Notes

The first step is to ensure the Product Development Kit (PDK) is fine-tuned and well supported.  Fine-tuned means current and new users are setup properly for the project.  All required libraries are available with verification flows tested and samples available.  Well supported means PDK documentation is available and as complete as possible.  

1) How long a layout designer spends understanding Design Rule Check (DRC) rules is directly proportionate to design rule manuals and examples being made available. 

2) Device placements will be made accurately the first time if auto cell abutment “Servers” are working properly.  

3) Routing goes considerably faster when metal patterning and via placement tools like “Area Via” are available and working. 

Floor Planning

The best way to begin a floor plan is with an area estimate that has been researched and studied well.  Large layout circuits and sub circuit layout designers need to know up front what pin, power, and timing constraints are.  This also helps the process of chip level integration go smoother.

Next and most important floor planning consideration is poly density.  For example, One large op-amp could use the same space as one small op-amp and a cluster of 100 logic devices.  A mock floor plan should be created using all required layout devices and standard cells.  This pays out significantly in utilizing left over floor space for real devices and not dummy fill.  The majority of power planning and I/O placements can begin at this point. Ideally, the integrator (or integration team) can pass down the lower blocks.  That usually leads to fist time completion and little re work.

OD & PO Grids

A finFET layout cell absolutely requires the use of OD and PO grids.  Metal grids are highly recommended.  These grids are purposely faded so layout designers can differentiate the grids from the actual layers.    

Device Placement

When placements are made the designer must ensure all diffusion (OD) is on the vertical fin grid.  Likewise, the poly (PO) should align with the horizontal fin grid.  There also needs to be an even number of PO stripes going across an entire array of poly stripes.

 To help with accurate placement, we use drawn boundary layers.  prBoundary.drawing and finBound.fb1 primarily.   Left and right sides of the finBound.fb1 should be adjacent to the prBoundary.drawing layer.   Top and bottom of finBound.fb1 layer must be inside the prBoundary.boundary layer. 

When placing these finFet pCells a Virtuoso Cad Designer is in a 2d world.  They will not see the “Fins” on the devices.  Unlike regular mosfet devices, which have “Source, Gate & Drain” laid out sort of perpendicularly,  finFet pCells connect parallel.  So while placements are being made, Source, Gate and Drain positions must be considered carefully.

With all of these concepts well understood the initial device placement can proceed.   It is imperative the design block be verified through DRC before main routing takes place. Issues such as density are extremely complex and require much adjustment to the base layers.  It should be of great concern if the cell is too small for density windows and therefore will not show any issues. That is until that cell is used at another level up. Some of these density issues had to be corrected and extensive re-work was required

Common guidelines for analog Device Placement require matching or mirroring need to be applied.  Both custom Analog and Digital circuits must have initial ideas established for device placements.   Floor planning should always begin at the highest level possible.  It seems that 90% of rework gets performed because this activity was not performed.  Initial placement ideas should be followed by identifying pin location constraints as they effect device placement locations.  Next, the nWell, pWell and any isolation scheme must then be established. Bulk connections (or back gates or gate ties) must be added.   Finally, dummies need to be instantiated and preferably accounted for in the schematics. 

Cut Layers

Cut layers are required for many types of layout.  But they can be critical when combining device groups and saving floor space.  During placement and routing, these layers can be crucial to completing a layout block.

Running Placement Level DRC

No matter how simple the block appeared (IE: Simple Level Shifter), odds are high that unaccounted for DRC errors will occur.  Since the average DRC run uses over 7000 rules, one would expect this to happen.  As discussed above, there are many forms of density violations and all should be considered based on the level you are working.  If the block you are working on is small, perhaps density DRC errors should be waved.  

In example, I had a block with many 8nm devices all brought together.  But the area they took was half the size of minimum poly area.  It also turned out that this block was the only 8nm device block in a massive block.  Since 8nm size requires at least 2 microns worth of strips horizontally and 36 square microns minimum area, those density errors do require attention and will not be “Fixable” further up the hierarchy.  Even using density fill. 

In another example, I aligned devices along a poly array and utilized the layer “CPO” (cut poly). That way the poly stripes could stay in place and not short out with each other. This worked great until the next level up where not so much CPO was used in the other blocks. This caused a gradient error DRC showing to be over maximum CPO density rules. Once again, lower level rework had to be performed. Absolute bottom line is density violations must be considered in great detail.

Routing

Once placement DRC is complete, routing can be performed.  Within the following paragraphs there are core concepts which must be considered before routing begins. 

Metal grid use with Cadence Work Space Patterning (WSP) tools makes custom routing much easier.  Layout designers can quickly change large arrays of color patterns.  These grids are purposely faded so layout designers can differentiate the grids from the actual layers.    

The mask designer should perform a DRC check after any large route or large group of routes have been created.  Just like with device placement, possibilities for unaccounted DRC error issues exponentially grow with every connection made.  

All metal objects must be rectangular.  No exceptions.  These rectangular objects are limited in width and sometimes required to be set on a grid designated for that metal.  IE:  Metal 1 widths can only be 20nm, 60nm, 76nm, 110nm, 120nm and 180nm.  Any other widths are not allowed.       

In order to connect metal to deep sub micron devices,  lower level metals (M0, M1, M2, M3 typically) must have “Mask A” or “Mask B” color properties.  When a wire gets laid out (created) for any type of semiconductor, a bleeding effect occurs causing jagged edges.  With large width metals this does not really matter much.  But when the required widths get small enough, this jagged edge really matters.  These are corrected through an etching step which clears the way for another metal of the same like to be laid down next to and in parallel.  It should be noted that the mask 2 is slightly less resistive than mask 1.  The physical design teams actually utilize this in order to alleviate start and stop time errors.

While creating routes, the mask designer designates (assigns) and locks colors to the rectangular metal objects (and vias) representing metal mask “A” or metal mask “B”.    Every object requires a locked mask color designation.   Once these color’s become established and locked the DRC rules will allow for significantly close like metal lines.    IE: A mask designer has 2 Parallel 20nm metal1 lines run from one place to another in their circuit ( about 1 micron).   The minimum space between these metal1 lines if they were the same mask color would be 120nm.  If one of those lines are designated and locked as “MaskA” (or highlighted in dark red) and the other parallel 20nm line is designated and locked as “MaskB” (or highlighted in dark green), minimum space requirement would drop significantly.  

With this process you can use square and rectangular VIA’s to best optimize your connections. That helps, but the MD needs to create cut layers which initially meet DRC requirements which are extensive.   Routing lower level metals with multiple mask options creates a 2 way perspective on metal spacing’s and via enclosures.  

Via creation is best performed utilizing auto creation as much as possible.  This can help right away with potential DRC issues like VIA density or “Three VIA in a row” errors.

Completion

If the mask designer utilizes Cadence Virtuoso XL specialized tool “Annotation Brower” combined with “Layout Extraction” then LVS stage will have minimum issues.  When utilizing layout extraction it is important to remember that pCells and instantiated macro’s can lose their true connectivity.  

If the PDK works, is well supported and the mask designer utilizes these notes and instructions,  productivity will be maximized.